Apparatus and methods of integrated-circuit device testing

ABSTRACT

A motherboard device (MB) interface board (DIB) configured as universal interface to a family of integrated circuit (IC) devices provides the electrical connectivity to automated test equipment (ATE) and physical mating commonality with an IC device handler for reduced time to market and enhanced economy for design validation and production verification testing. In particular, use of one or more daughter cards (DC) that mount to the MB DIB avoid redesign of the entire DIB assembly for a new IC design. Each DC can be more quickly designed at a lower cost than the entire DIB assembly, enabling replacement of any defective site. The DC increases the available surface area for mounting of support components for the device under test (DUT).

CLAIM OF PRIORITY UNDER 35 U.S.C. §119

The present Application for Patent claims priority to ProvisionalApplication No. 60/975,091 entitled “AUTOMATIC TEST EQUIPMENT MODULARITYIMPROVES GAGE PERFORMANCE: A MOTHERBOARD AND DAUGHTERCARD CONCEPT” filed25 Sep. 2007, and assigned to the assignee hereof and hereby expresslyincorporated by reference herein.

FIELD OF INVENTION

The present application relates generally to semiconductor processesand, more specifically, to methods and systems to increase performancethrough improved device interface board design and automatic testequipment modularity.

BACKGROUND

In order to be competitive, semiconductor manufacturers strive to reducethe time to market for design, manufacture, validation and delivery ofintegrated circuit (IC) devices. In addition, to time, significantdevelopment has been invested in making each step in the process moreeconomical, such as validation testing. In particular, automated testequipment (ATE) is programmed to support, stimulate and sense operatingparameters of a given IC device. A handler positions each IC device fortesting by the ATE, and the testing results in separately binning goodand bad IC devices.

Significant hardware investment has been made in ATE and handlerequipment suitable for validation testing of a wide range of IC devices.For example, ATE incorporates a wide array of capabilities for providingradio frequency (RF) signals and sensing, various digital signal inputsand outputs, etc. In order to multiply the throughput of such ATE,typically each ATE can simultaneously test a plurality of IC devices,supported by handlers designed for simultaneously placing and retrievingthese IC devices under test (DUT). A degree of standardization in suchequipment occurs in order to make them more economical and to reduce thetraining time required for programmers of such ATE and handlers. To thatend, each validation testing effort has to be adapted to the electricalcapabilities and constraints of the ATE and to the hardwareconfiguration and limitations of the handler.

A typical device interface board (DIB) design used by all semiconductormanufacturers consists of a printed circuit board (PCB) with all theessential supporting components and circuits along with a test socket.Test software is then written to provide instructions to the ATE on thestimulus to provide and the measurements to make. Ultimately, a decisionwill be made to distinguish a good part from a bad part, also commonlytermed as binning. A DIB may come in different shapes and sizes, but theconcept is the same.

Although standardization of ATE and handlers is desirable, a challengeis presented by an ongoing effort to make IC devices smaller and morecapable, which often means increasing complexity in interfacing to theIC device (e.g., increased pin count, increased numbers of inputs andoutputs, etc.). This increased complexity is accommodated by designing acustom DIB that mounts to the ATE for providing one or more custom testsites for receiving IC devices from the handler. A printed circuit board(PCB) of the DIB is increasing in the number of layers (e.g., 22, 24,etc.) that are required to provide the required connectivity andsupporting signals. Area available for mounting support components(e.g., lumped electronic components) is generally limited to anunderside of the PCB because an upper surface is limited by clearancefor the handler and for docking sites.

Another challenge is that the multiple test sites on the DIB requiretraces that perform identically so that shared signals test each ICdevice identically. The large size of the DIB and the traces, with someby necessity being routed differently in length, make such designsproblematic.

Even if these constraints can be satisfied, the large size of the PCBfor the DIB makes design of each layer time consuming, with currentbenchmarks indicating that an experienced design engineer requires oneday per layer. Thus, it is not uncommon for the length of time requiredto design a DIB to become the critical path rather than the manufactureof a new IC device. This is increasingly a challenge, as conventionalDIBs need to have additional layers to support complex IC devices.

Yet another challenge is that manufacturing costs are based uponassumptions that each ATE is being operated at capacity. However, whenone test site fails on a multiple test site DIB, the rate of validationtesting goes down. Each DIB has a cost that is prohibitive inprovisioning spares and is expensive to diagnose and repair. Forexample, it is common for a DIB to currently cost $30,000 for areplacement.

Towards the end of the hardware and software development cycle,engineers need to perform a Gage study to determine repeatability (i.e.,data variation when tested multiple times) and reproducibility (i.e.,data reproduction using multiple correlated testers), which provides asindicators of quality and stability of the final test solution. Sampledata is collected across multiple ATE testers, DIBs, and devices toderive the mean and standard deviation from which a user can determinethe acceptability of the final test solution. In the detaileddescription, embodiments will be presented to improve overallperformance by yielding better Gage results. Improvements in performanceas shown in a Gage study will correlate to the speed of which a productcan be brought to market/production as well as the quality of the testsolution, all of which fortifies a company's leadership in a specificmarket space. It is thus a challenge to make corrections to satisfy aGage study if a change to the DIB is necessary.

SUMMARY

The following presents a simplified summary in order to provide a basicunderstanding of some aspects of the disclosed aspects. This summary isnot an extensive overview and is intended to neither identify key orcritical elements nor delineate the scope of such aspects. Its purposeis to present some concepts of the described features in a simplifiedform as a prelude to the more detailed description that is presentedlater.

In accordance with one or more aspects and corresponding disclosurethereof, various aspects are described in connection with providingdevice interfaces for design validation testing and productionverification testing of integrated devices. In particular, these deviceinterfaces maintains electrical connectivity to automated test equipment(ATE) and physical mating commonality with an IC device handler yetachieves reduced time to market and enhanced economy. In particular, acommon device interface board (DIB) can be used universally for a familyof integrated devices, including a new design that is not yet complete.A much smaller and less expensive daughter card is designed when theintegrated device design is available, avoiding the time and expense ofdesigning, manufacturing and repairing a conventional unitary DIB.

In one aspect, an apparatus is provided for reduced time to market andenhanced economy for design validation and production verificationtesting. A common device interface board (DIB) is sized for andelectrically interfaced for being received by automated test equipmentand presents a card-mounting fixture. A daughter card is attached to thecard-mounting fixture and electrically interfaced thereby to theautomated test equipment via the common DIB to form a DIB assembly. Atest site attached to the daughter card and positioned by the DIBassembly receiving integrated devices for testing from a handler.

In another aspect, a method is provided for reduced time to market andenhanced economy for design validation and production verificationtesting. Creating a common device interface board (DIB) that is sizedfor and electrically interfaced for being received by automated testequipment and presenting a card-mounting fixture can be achieved inadvance of a design for an integrated device. A DIB assembly is formedby attaching a daughter card to the card-mounting fixture andelectrically interfacing thereby to the automated test equipment via thecommon DIB. Then testing can be performed by inserting an integrateddevice with a handler into a test site attached to the daughter card.

In yet another aspect, an apparatus for reduced time to market andenhanced economy for design validation and production verificationtesting provides means for creating a common device interface board(DIB) sized for and electrically interfaced for being received byautomated test equipment and presenting a card mounting fixture. Inaddition, means are provided for attaching a daughter card to thecard-mounting fixture and electrically interfacing thereby to theautomated test equipment via the common DIB to form a DIB assembly.Further, means are provided for inserting an integrated device with ahandler into a test site attached to the daughter card.

To the accomplishment of the foregoing and related ends, one or moreaspects comprise the features hereinafter fully described andparticularly pointed out in the claims. The following description andthe annexed drawings set forth in detail certain illustrative aspectsand are indicative of but a few of the various ways in which theprinciples of the aspects may be employed. Other advantages and novelfeatures will become apparent from the following detailed descriptionwhen considered in conjunction with the drawings and the disclosedaspects are intended to include all such aspects and their equivalents.

BRIEF DESCRIPTION OF THE DRAWINGS

The features, nature, and advantages of the present disclosure willbecome more apparent from the detailed description set forth below whentaken in conjunction with the drawings in which like referencecharacters identify correspondingly throughout and wherein:

FIG. 1 illustrates a schematic diagram with a vertical cross sectionportion of a handler positioning two integrated circuit (IC) devicesunder test (DUT) in corresponding daughter card sites independentlyconnected to a motherboard of a device interface board (DIB) assembly.

FIG. 2 illustrates a perspective view of the DIB assembly of FIG. 1 witha four daughter card configuration.

FIG. 3 illustrates an exploded, detail view of a daughter card and anunderlying portion of the motherboard of the DIB assembly of FIG. 1.

FIG. 4 illustrates a top and a bottom isometric view of the daughtercard of FIG. 1.

FIG. 5 illustrates a Gantt chart for a methodology for designing an ICdevice and providing for the validation testing in production with aconventional DIB.

FIG. 6 illustrates a Gantt chart for a methodology for designing an ICdevice and for providing for the validation testing in production with aDIB assembly.

FIG. 7 illustrates a flow diagram of a methodology for IC devicetesting.

DETAILED DESCRIPTION

The cost of DIB design increases as the complexity of chips increaseover time, which has lengthened time to market, raised the cost ofhardware, forced cutting of edge vendors, and increased the need forhighly skilled engineers. More CAD personnel are required to maintainthe same rate at which products are developed due to the extended timerequired for complex routing and reviews. DIB complexity has increased,for example including 22 layers, to accommodate smaller high-densitypackages with increased turnaround times from the board fabricationmanufacturer. Large-scale chip integration requires careful DIB routingto ensure performance and testability, all of which requires teams ofengineers for review and debug.

With commodity parts such as power management devices, price and cost isa gating factor in the success of a company. Cost of test contributionsto the bottom line are significant, and by finding innovative ways toaddress these issues, manufacturers can stay competitive.

The goal is to simplify the DIB design so that the time needed todesign, layout, build, and debug is also reduced. The simplificationprocess leads to cost reduction, reduced time to market, reduction inthe need for highly skilled engineers, increased modularity, promotionof standardization, and increases in testing performance and efficiency.

Since multiple devices (sites) are tested at the same time, each site isthus treated independently. By outlining each test site with animaginary rectangular box a separate daughter card can be created and anelectrical connection may be provided via a mating connector. By doingso, a “motherboard” becomes a universal or common board that can be usedwith all future PMIC devices. This lends to reusability and facilitatesthe debug process.

In an illustrative implementation, the daughter cards are then treatedindividually instead of as a group, such as the group of four on a priorart DIB. As such, the described aspects allow for the layout of one siteinstead of four, thereby reducing the CAD layout time by 75%,dramatically reducing the team review process, and improvingeffectiveness by making for a smaller design. Since each daughter cardis identical in layout, the performance characteristics of each site arethe same, which lends towards improved repeatability andreproducibility. This is evident in improved yields and reduced retestrates, as evidenced by several Gage studies. The debug process isshortened because there is less hardware to debug and the daughter cardscan go on any test site and any motherboard, which drasticallysimplifies this process by being able to reduce the number of variables.

While in production, there is no longer a need for debug if a site goesdown. Instead of attempting to debug a prior art unitary DIB withmultiple sites, the described aspects allow for a new pre-validateddaughter card, which is independent from the DIB, to be used as areplacement, allowing the old daughter card to be discarded. This willprove to be much more cost effective as the price of daughter cardreplacements is significantly cheaper than engineering debug time andresource allocation. Otherwise, the entire DIB needs to be sent back fortimely debug and additional spares are required as a backup, furtherincreasing cost and test site maintenance. Further improvements areeasily made since only the daughter cards needs to be changed andimproved instead of the entire DIB. This makes hardware deployment onany project that much easier.

A motherboard device interface board (DIB) configured as a universalinterface to a family of IC devices, including but not limited to, forexample, power management integrated circuits (PMIC), may includesymmetry of the placement and mating structures for modularity,simplicity, and maximum configurability. The end user can hand pick thebest of the bench to yield improved performance and robustness; of whichall contributes to the company's bottom line and strengthen its marketposition in producing quality product in a short time withoutcompromising on quality.

Various aspects are now described with reference to the drawings. In thefollowing description, for purposes of explanation, numerous specificdetails are set forth in order to provide a thorough understanding ofone or more aspects. It may be evident, however, that the variousaspects may be practiced without these specific details. In otherinstances, well-known structures and devices are shown in block diagramform in order to facilitate describing these aspects.

In FIG. 1, a validation test apparatus 100 for integrated circuit (IC)devices under test (DUT) 102 advantageously utilizes a device interfaceboard (DIB) assembly 104 that increases commonality and universality foreconomy by utilizing a universal motherboard (“common device interfaceboard”) 106. Additionally, apparatus 100 is readily configurable andrepairable with one or more (two are illustrated in FIG. 1) separate andindependent daughter cards 108 customized for the design of the IC DUT102.

The motherboard 106 can include a multi-layer printed circuit board(PCB) 110 that provides sufficient electrical connectivity to a testconnector 112 for all of the required stimuli, support and sensing froman automated test equipment (ATE) 114. For clarity, theseinterconnections are depicted functionally as being interfaced to radiofrequency (RF) components 116, power components 118, digital switchingcomponents 120 and sensors 122 under the control of an automatic testequipment (ATE) processor 124 executing an ATE test program 126. Thetraces and inter-layer connections (not shown) that provide thesecommunication paths to the test connector 112 can be generalized toprovide symmetrical support to each test site 128 provided by the one ormore daughter cards 108, as well as a range of possible signals toaccommodate a broad range of currently produced IC devices 102 as wellas those foreseeable in the future.

A pair of stiffener rails 130 attached to a top surface 132 of the PCB110 of the motherboard 106 supports a respective daughter card 108 thatis registered by a pair of fasteners 134, each passing through themotherboard, rail 130 and one side of a daughter card PCB 136. Thespacing provided by the stiffener rails 130 provides for downwardlyprojecting male connectors 138 on an undersurface 139 the daughter card108 to be received in upwardly projecting female connectors 140 on thetop surface 132 of the motherboard 106, laterally positioned outside ofthe rails 130. Spacing is also provided for mounting fixtures 142 on theundersurface of the daughter card PCB 136 fastened to a test site base144 on an upper surface 145 having upwardly open guide holes 146 about acentral aperture 148 for receiving one of the IC DUTs 102. Theundersurface 139 of the daughter card PCB 136 also provides area forplacing support components 148 needed for the operation of the IC DUT102 (e.g., RLC components).

A handler 150 horizontally and vertically positions a chuck 152 for eachtest site 128, registered by downward pins 154, with the IC device 102inserted into the test site 128 by a plunger 156.

In FIG. 2, an exemplary DIB assembly 104 includes a motherboard 106mounted to a metal stiffening tray 158 that provides mounting provisionsto a handler (not shown in FIG. 2). Four daughter cards 108 are shown,each capped by a handler chuck 152.

In FIG. 3, an exemplary DIB assembly 104 provides a modular designwherein a relatively small daughter card 108 can be customized for thedesired functionality of the test site 128 and can be physically removedand made independent of the remainder of the common device interfaceboard or universal motherboard 106. Mechanical constraints andconsiderations maintain the physical integrity for this solution. Forexample, the support rails 130 receive the loads from the handler (notshown in FIG. 3). The fasteners 134 can be received in internallythreaded extensions 160 to guide and register male connectors 138 of thedaughter card 108 into female connectors 140 of the motherboard 106.

The low profile mating connectors 138, 140 provide high performanceelectrical connections for the device under test (DUT). The supportrails 130 provide durable mechanical support from the constant chipinsertion forces from the handler as well as vibration dampeningcharacteristics to protect the mating connectors 138, 140 from wear overtime. The materials may be chosen so as to expand and contract at thesame rate as the DIB.

In FIG. 4, a daughter card 108 includes an upper surface 145 having aguide hole 170 for registering to a motherboard (not shown in FIG. 4).Daughter card 108 further includes a square test site base 172 withcorner recessed fastener receptacles 174 and a pair of guide apertures176 longitudinally positioned about a test site receptacle 178. Thedaughter card 108 is also depicted having an X-shaped mounting plate 180on the undersurface 139 of the daughter card 108 for attaching the base172. On each longitudinal end of the daughter card 108, a respectiveguide pin 182 flanked by male connectors 184 with locking flanges 186projects from the undersurface 139 for attachment to the motherboard.Surface 188, which may be utilized for mounting support components, isprovided between the connectors 184 and the X-shaped mounting plate 180.

In FIG. 5, a conventional methodology, depicted at 200 presentschallenges due to a unitary DIB whose configuration has to wait untilthe IC is designed (block 202). While the IC is being manufactured inblock 204, supporting development has to be completed in order not tojeopardize the time to market goals. One such development is to designand code ATE code for testing in block 206. In parallel with theseefforts, an ATE DIB having a unitary design is developed in block 208.In order to support a complex IC, the number of layers can be 22, 24 ormore. Due to the large size of the unitary DIB with perhaps a pluralityof test sites per DIB, an experienced design engineer can require abouta day per layer to design the DIB. Once the DIB design is completed, theDIB is manufactured in block 210. Due to the challenging operatingconditions often employed in verification testing, the DIB and other ATEequipment are Gage tested in order to verify that the test results arereliable and repeatable with an acceptable degree of variations in block212. Then the ICs can be tested to validate the design or to verify theproduction in block 214. Given the complexity and cost of the DIB, it isfrequently the case that a test site on the DIB fails. Rather thantaking one ATE setup out of production, often this DIB continues to beused with one test site left unused, thus extending the time required toperform a test, as depicted at block 216.

In FIG. 6, a methodology 300 benefits from a DIB assembly of amotherboard and one or more independent daughter cards. Thus, while anIC is being designed in block 302, a standard or universal motherboard(MB) DIB can be prepared or provisioned, as depicted at 304. Inparticular, a pre-existing MB DIB can be readied or a new MB DIB can bedesigned and fabricated with excess capabilities to accommodate afuture, incomplete IC design. With the IC design complete andmanufacture of a semiconductor underway as depicted in block 306, thesupporting developments can be expedited without endangering thecritical path of design, testing, debugging and verification of the ICitself. In particular, the ATE code is designed and written in block308. In parallel with the code, a single daughter card portion of theDIB assembly is designed in block 310. Given the small size of each testsite, and the fact that each test site has a standard form, fit andfunction, a less experienced design engineer is readily able to design amodular PCB with supporting electronic components in a much smaller spanof time. These factors also result in a shorter and less expensivemanufacturing process for the daughter card at block 312 and Gagetesting of the resulting testing apparatus in block 314. In addition,when design validation or production verification testing begins inblock 316, failures of a particular daughter card can be readilyremedied with a provisioned spare. The provisioned space, which is aninexpensive replacement, provides an economic advantage over the delaysand expenses in shipping and repairing a large conventional unitary DIB.

In FIG. 7, a methodology 400 for IC device testing that leverages theconsiderable investment to date in ATE and handler equipment is enhancedby use of a DIB assembly of a motherboard and one or more independentdaughter card(s) as compared to a conventional unitary DIB. In block402, the modest design and manufacturing effort required for a daughtercard can be performed, taking advantage of the existing universalmotherboard. Then testing can commence. In particular, one or moredaughter cards are attached to the motherboard to form a DIB assemblythat is docked to the ATE in block 404. The ATE program code is loadedinto the ATE in block 406. Meanwhile, the untested devices are placedinto trays in block 408 that are then placed into the handler in block410. The handler can then be docked to the ATE to commence designvalidation or production verification testing in block 412. Since thedaughter cards of the DIB assembly are subject to damage from wear,impact and vibration more so than the supporting motherboard, instancesmay occur in block 414 when a test site fails, which can be quickly andeconomically remedied by replacing the failed daughter card. As DUTsleave testing, the good and bad tested devices are binned for deliveryor rework/scrap, respectively, in block 416.

The word “exemplary” is used herein to mean serving as an example,instance, or illustration. Any aspect or design described herein as“exemplary” is not necessarily to be construed as preferred oradvantageous over other aspects or designs.

In view of the exemplary systems described supra, methodologies that maybe implemented in accordance with the disclosed subject matter have beendescribed with reference to several flow diagrams. While for purposes ofsimplicity of explanation, the methodologies are shown and described asa series of blocks, it is to be understood and appreciated that theclaimed subject matter is not limited by the order of the blocks, assome blocks may occur in different orders or concurrently with otherblocks from what is depicted and described herein. Moreover, not allillustrated blocks may be required to implement the methodologiesdescribed herein. Additionally, it should be further appreciated thatthe methodologies disclosed herein are capable of being stored on anarticle of manufacture to facilitate transporting and transferring suchmethodologies to computers. The term article of manufacture, as usedherein, is intended to encompass a computer program accessible from anycomputer-readable device, carrier, or media.

Those skilled in the art will understand that information and signalsmay be represented using any of a variety of different technologies andtechniques. For example, data, instructions, commands, information,signals, bits, symbols, and chips that may be referenced throughout theabove description may be represented by voltages, currents,electromagnetic waves, magnetic fields or particles, optical fields orparticles, or any combination thereof.

In one or more exemplary embodiments, the functions described may beimplemented in hardware, software, firmware, or any combination thereof.If implemented in software, the functions may be stored on ortransmitted over as one or more instructions or code on acomputer-readable medium. Computer-readable media includes both computerstorage media and communication media including any medium thatfacilitates transfer of a computer program from one place to another. Astorage media may be any available media that can be accessed by acomputer. By way of example, and not limitation, such computer-readablemedia can comprise RAM, ROM, EEPROM, CD-ROM or other optical diskstorage, magnetic disk storage or other magnetic storage devices, or anyother medium that can be used to carry or store desired program code inthe form of instructions or data structures and that can be accessed bya computer. Also, any connection is properly termed a computer-readablemedium. For example, if the software is transmitted from a website,server, or other remote source using a coaxial cable, fiber optic cable,twisted pair, digital subscriber line (DSL), or wireless technologiessuch as infrared, radio, and microwave, then the coaxial cable, fiberoptic cable, twisted pair, DSL, or wireless technologies such asinfrared, radio, and microwave are included in the definition of medium.Disk and disc, as used herein, includes compact disc (CD), laser disc,optical disc, digital versatile disc (DVD), floppy disk and blu-ray discwhere disks usually reproduced data magnetically, while discs reproduceddata optically with lasers. Combinations of the above should also beincluded within the scope of computer-readable media.

It should be appreciated that any patent, publication, or otherdisclosure material, in whole or in part, that is said to beincorporated by reference herein is incorporated herein only to theextent that the incorporated material does not conflict with existingdefinitions, statements, or other disclosure material set forth in thisdisclosure. As such, and to the extent necessary, the disclosure asexplicitly set forth herein supersedes any conflicting materialincorporated herein by reference. Any material, or portion thereof, thatis said to be incorporated by reference herein, but which conflicts withexisting definitions, statements, or other disclosure material set forthherein, will only be incorporated to the extent that no conflict arisesbetween that incorporated material and the existing disclosure material.

1. An apparatus for reduced time to market and enhanced economy fordesign validation and production verification testing, comprising: acommon device interface board (DIB) sized for and electricallyinterfaced for being received by automated test equipment and presentinga card mounting fixture; a daughter card attached to the card mountingfixture and electrically interfacing thereby to the automated testequipment via the common DIB to form a DIB assembly; and a test siteattached to the daughter card and positioned by the DIB assembly forreceiving integrated devices for testing from a handler.
 2. Theapparatus of claim 1, further comprising a disengagable attachmentbetween the daughter card and the common DIB for repair replacement. 3.The apparatus of claim 1, wherein the common DIB further comprises aplurality of card mounting fixtures; and a plurality of daughter cardsattached respectively to the corresponding plurality of card mountingfixtures, presenting test sites aligned for receiving a plurality ofintegrated devices simultaneously from handler for concurrent testing.4. The apparatus of claim 3, further comprising a disengagableattachment between each daughter card and the common DIB for replacementof a failed daughter card to facilitate full-rate testing.
 5. Theapparatus of claim 3, wherein each card mounting fixture is identicaland each daughter card is identical for simplified design andprovisioning.
 6. The apparatus of claim 1, wherein the common DIB andthe daughtercard are positioned so as to define a spacing sufficient formounting electronic components between an undersurface of the daughtercard and an upper surface of the common DIB, and further comprisingelectronic components mounted on the undersurface of the daughter cardfor electrically supporting the integrated device under test.
 7. Amethod for reduced time to market and enhanced economy for designvalidation and production verification testing, comprising: creating acommon device interface board (DIB) sized for and electricallyinterfaced for being received by automated test equipment and presentinga card mounting fixture; attaching a daughter card to the card mountingfixture and electrically interfacing thereby to the automated testequipment via the common DIB to form a DIB assembly; and inserting anintegrated device with a handler into a test site attached to thedaughter card.
 8. The method of claim 7, further comprising disengagingthe attachment between the daughter card and the common DIB for repairreplacement with another daughter card.
 9. The method of claim 7,further comprising: creating the common DIB with a plurality of cardmounting fixtures; attaching a plurality of daughter cards respectivelyto the corresponding plurality of card mounting fixtures; andsimultaneously inserting a plurality of integrated devices with thehandler for concurrent testing in a respective test site on eachdaughter card.
 10. The method of claim 9, further comprising disengagingan attachment between one failed daughter card and the common DIB forreplacement with another daughter card to facilitate full-rate testing.11. The method of claim 9, further comprising creating an identicalplurality of card mounting fixtures and an identical plurality ofdaughter cards for simplified design and provisioning.
 12. The method ofclaim 7, further comprising creating the card mounting fixture of thecommon DIB with a support structure spacing an undersurface of thedaughter card from an upper surface of the common DIB, the spacingcorresponding to low profile electrical connectors between the daughtercard and the common DIB and sufficient for electronic components mountedon the undersurface of the daughter card for electrically supporting theintegrated device under test.
 13. An apparatus for reduced time tomarket and enhanced economy for design validation and productionverification testing, comprising: means for creating a common deviceinterface board (DIB) sized for and electrically interfaced for beingreceived by automated test equipment and presenting a card mountingfixture; means for attaching a daughter card to the card mountingfixture and electrically interfacing thereby to the automated testequipment via the common DIB to form a DIB assembly; and means forinserting an integrated device with a handler into a test site attachedto the daughter card.
 14. The apparatus of claim 13, further comprisingmeans for disengaging the attachment between the daughter card and thecommon DIB for repair replacement with another daughter card.
 15. Theapparatus of claim 13, further comprising: means for creating the commonDIB with a plurality of card mounting fixtures; means for attaching aplurality of daughter cards respectively to the corresponding pluralityof card mounting fixtures; and means for simultaneously inserting aplurality of integrated devices with the handler for concurrent testingin a respective test site on each daughter card.
 16. The apparatus ofclaim 15, further comprising means for disengaging an attachment betweenone failed daughter card and the common DIB for replacement with anotherdaughter card to facilitate full-rate testing.
 17. The apparatus ofclaim 15, comprising means for creating an identical plurality of cardmounting fixtures and an identical plurality of daughter cards forsimplified design and provisioning.
 18. The apparatus of claim 13,further comprising means for creating the card mounting fixture of thecommon DIB with a support structure spacing an undersurface of thedaughter card from and upper surface of the common DIB, the spacingcorresponding to low profile electrical connectors between the daughtercard and the common DIB and sufficient for electronic components mountedon the undersurface of the daughter card for electricity supporting theintegrated device under test.